An interrupt is hardware asking for attention in the middle of anything. This diagram follows one from the wire: the device asserts an IRQ line, the interrupt controller maps it to a vector, the CPU saves minimal state and jumps through the IDT, and the top-half handler acknowledges the device and defers the real work. The ordering matters because the split is the design: top halves must be short — they run with interrupts masked on their CPU — so protocol processing and I/O completion are deferred to bottom halves (softirqs and workqueues) that run with interrupts enabled. The done stage shows iretq restoring the interrupted task, which never noticed anything except a few cycles of jitter.
Interrupt Handling
Interrupt handling: IRQ to vector, IDT dispatch, top-half acknowledge, bottom-half deferral, and iret restore.
The Runtime Theory Team07 stages
trace / request.md
readyHardware — a NIC, a disk controller, the timer — asserts an interrupt line because it needs attention: data arrived, an I/O completed, a tick elapsed.