A page fault is how the OS makes virtual memory honest: the hardware asks for a translation, finds the page missing, and the kernel materializes it before the same instruction runs again. This diagram follows the full sequence — TLB miss, hardware page-table walk, a leaf PTE with the present bit clear, the #PF trap, and the kernel classifying the fault against the process's VMAs. Minor faults are cheap: the page already exists in the page cache or needs only zeroing or a COW copy. Major faults read from disk or swap, sleeping the task for milliseconds. The ordering matters because classification determines the cost. The done state: the PTE is installed, the TLB refilled, and the faulting instruction retried — this time succeeding.
Page Fault Handling
Page fault handling: TLB miss, page-table walk, minor vs major faults, PTE installation, and instruction retry.
The Runtime Theory Team08 stages
trace / request.md
readyThe CPU tries to translate a virtual address and the TLB has no entry for it. The MMU starts a hardware page-table walk through the four levels.