Explain virtual memory and why every process sees the same addresses

This question tests whether you know that virtual memory is a mapping mechanism, not a storage abstraction. The interviewer wants the MMU and the page table — not "each process thinks it owns all the RAM."

The mental model: every memory access the CPU performs is to a virtual address. The MMU translates it to a physical address by walking a per-process page table. Because each process has its own page table, the same virtual address in two processes is just two entries pointing at two different physical frames — or at nothing.

Walk through the mechanism on x86-64. The page table is four levels deep (PGD, PUD, PMD, PTE), rooted at a physical address in the CR3 register, which is loaded on every process context switch. A virtual address splits into index bits for each level plus an offset into the 4KiB page. The MMU walks the levels, reads the final PTE, and the frame bits give the physical page. The TLB caches recent translations so the walk usually happens once per page, not per access. That's why TLB flush on a context switch is a real cost: without PCID tags, switching CR3 means the next accesses all miss.

Why every process sees the same addresses: the address space layout is a convention, not hardware. Kernel space occupies the same high half (above 0xffff800000000000) in every process because it's mapped into every page table — that's how syscalls can run in the process's context. Userspace regions like the stack at 0x7ffc... are the same virtual addresses in every process, but each process's PTE for that address points at its own physical pages. When two processes load the same shared library, the kernel maps the same physical page into both page tables — sharing with zero copying.

Tradeoffs and edge cases worth naming:

• Protection bits live in the PTE: user/supervisor, read/write/execute. The hardware enforces them on every access, which is how a wild pointer becomes SIGSEGV instead of corrupting another process.
• ASLR randomizes the layout, so the addresses are only "the same" as a convention.
• Sparse address spaces are free: you can mmap a 1TB region, and only the pages you touch get PTEs and physical frames.
• TLB misses on a process switch are mitigated by PCID — a tag that lets old translations survive the CR3 swap.

A strong closing line: virtual memory is per-process page tables plus a hardware walker; the identical addresses are the illusion, and different page tables are the reality.