Why does sequential array access outperform random access?

A strong answer

A strong candidate frames Why does sequential array access outperform random access? around the exact memory layout, compiler semantics, and hardware execution model covered in CPU Cache Hierarchy: L1/L2/L3 Topologies, Cache Lines, and Data Locality. Explain spatial locality, cache line prefetching, and how sequential access fills cache lines efficiently.

Modern CPUs execute instructions at clock speeds between 3.5 GHz and 5.0 GHz. A single CPU clock cycle takes roughly 0.2 to 0.3 nanoseconds. In a single cycle, modern superscalar cores can retire 4 to 8 instructions.

Both functions execute identical arithmetic operations:

• Exactly 4096 * 4096 = 16,777,216 memory reads.
• Exactly 16,777,216 additions.
• Time complexity is analytically identical: O(N^2).

In a production interview, always connect the specification rule to its concrete runtime consequence: state what lives on the stack versus the heap or static storage segment, how the compiler or operating system validates alignments, lifetimes, and error codes, and what happens under adversarial or boundary inputs (such as zero-length buffers, integer overflow, concurrent mutation, or partial I/O). Backing your explanation with a small trace of register/memory state transitions immediately separates senior systems engineers from candidates who only memorized syntax.

What the interviewer is listening for

• Mastery of core invariant: Differentiate L1, L2, L3 cache topologies, access latencies, and cache line transfers.
• Mastery of core invariant: Exploit spatial and temporal locality to maximize CPU memory bandwidth.
• Mastery of core invariant: Deconstruct physical memory addresses into Tag, Set Index, and Offset bitfields.
• Hardware and ABI awareness: Explaining how sizes, alignments, calling conventions, or kernel boundaries behave on real 64-bit targets rather than relying on implementation-defined assumptions.
• Defensive engineering: Naming the exact compiler flags (-Wall -Wextra -Werror), static analyzers, or runtime sanitizers (-fsanitize=address,undefined,thread) that verify correctness in CI.

Common mistakes

• Explaining only surface syntax without tracing the underlying memory addresses, ownership lifetime, or kernel/user-space state transitions.
• Assuming undefined behavior (such as signed overflow, uninitialized reads, strict-aliasing violations, or dangling pointers) will "just work" because it passed an unoptimized -O0 debug build.
• Ignoring return codes, partial reads/writes, alignment padding, or cleanup paths when an allocation or syscall fails midway through a function.