Why do independent counters slow each other down on multicore hardware?

A strong answer

A strong candidate frames Why do independent counters slow each other down on multicore hardware? around the exact memory layout, compiler semantics, and hardware execution model covered in Caches and False Sharing: Layout for Speed. Explain cache lines, false sharing, and the alignas sharding fix with a scaling test as proof.

Before the fix the eight slots packed into one or two lines and every store bounced the line across cores. After alignas(64) each slot owns its line and the loop scales. The fix is one keyword plus measurement; the understanding is the whole lesson.

Eight threads can each run a tight loop with no shared state on paper and still scale poorly. No lock appears in the code. No atomic appears in the hot loop. Yet throughput stalls as thread count rises. That pattern points at the memory system rather than the algorithm. A scaling test makes it plain: one thread finishes fast, eight threads crawl per item. The honest harness catches this shape with interleaved trials and medians.

In a production interview, always connect the specification rule to its concrete runtime consequence: state what lives on the stack versus the heap or static storage segment, how the compiler or operating system validates alignments, lifetimes, and error codes, and what happens under adversarial or boundary inputs (such as zero-length buffers, integer overflow, concurrent mutation, or partial I/O). Backing your explanation with a small trace of register/memory state transitions immediately separates senior systems engineers from candidates who only memorized syntax.

What the interviewer is listening for

• Mastery of core invariant: Explain cache lines and why two counters can slow each other down.
• Mastery of core invariant: Use alignas and padding to separate hot fields.
• Mastery of core invariant: Fix a false-sharing slowdown with per-thread sharding.
• Hardware and ABI awareness: Explaining how sizes, alignments, calling conventions, or kernel boundaries behave on real 64-bit targets rather than relying on implementation-defined assumptions.
• Defensive engineering: Naming the exact compiler flags (-Wall -Wextra -Werror), static analyzers, or runtime sanitizers (-fsanitize=address,undefined,thread) that verify correctness in CI.

Common mistakes

• Explaining only surface syntax without tracing the underlying memory addresses, ownership lifetime, or kernel/user-space state transitions.
• Assuming undefined behavior (such as signed overflow, uninitialized reads, strict-aliasing violations, or dangling pointers) will "just work" because it passed an unoptimized -O0 debug build.
• Ignoring return codes, partial reads/writes, alignment padding, or cleanup paths when an allocation or syscall fails midway through a function.